Index of /llvm-10.0.1/test/CodeGen/RISCV

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]atomic-rmw.ll2020-07-07 12:21 569K 
[ ]vararg.ll2020-07-07 12:21 89K 
[ ]atomic-cmpxchg.ll2020-07-07 12:21 88K 
[ ]inline-asm-d-abi-names.ll2020-07-07 12:21 44K 
[ ]srem-vector-lkk.ll2020-07-07 12:21 44K 
[ ]inline-asm-abi-names.ll2020-07-07 12:21 43K 
[ ]inline-asm-f-abi-names.ll2020-07-07 12:21 43K 
[ ]rv64i-exhaustive-w-insts.ll2020-07-07 12:21 42K 
[ ]interrupt-attr.ll2020-07-07 12:21 40K 
[ ]calling-conv-ilp32-ilp32f-ilp32d-common.ll2020-07-07 12:21 37K 
[ ]urem-vector-lkk.ll2020-07-07 12:21 36K 
[ ]rv64m-exhaustive-w-insts.ll2020-07-07 12:21 34K 
[ ]atomic-load-store.ll2020-07-07 12:21 32K 
[ ]interrupt-attr-nocall.ll2020-07-07 12:21 27K 
[ ]float-br-fcmp.ll2020-07-07 12:21 23K 
[ ]double-br-fcmp.ll2020-07-07 12:21 22K 
[ ]rv64i-single-softfloat.ll2020-07-07 12:21 22K 
[ ]double-select-fcmp.ll2020-07-07 12:21 19K 
[ ]double-intrinsics.ll2020-07-07 12:21 18K 
[ ]double-arith.ll2020-07-07 12:21 17K 
[ ]calling-conv-lp64-lp64f-lp64d-common.ll2020-07-07 12:21 17K 
[ ]bswap-ctlz-cttz-ctpop.ll2020-07-07 12:21 16K 
[ ]float-intrinsics.ll2020-07-07 12:21 16K 
[ ]stack-realignment.ll2020-07-07 12:21 15K 
[ ]srem-lkk.ll2020-07-07 12:21 15K 
[ ]float-select-fcmp.ll2020-07-07 12:21 15K 
[ ]float-arith.ll2020-07-07 12:21 12K 
[ ]div.ll2020-07-07 12:21 12K 
[ ]double-fcmp.ll2020-07-07 12:21 12K 
[ ]float-bit-preserving-dagcombines.ll2020-07-07 12:21 12K 
[ ]calling-conv-ilp32d.ll2020-07-07 12:21 12K 
[ ]alu64.ll2020-07-07 12:21 11K 
[ ]calling-conv-ilp32-ilp32f-common.ll2020-07-07 12:21 11K 
[ ]select-optimize-multiple.ll2020-07-07 12:21 10K 
[ ]sext-zext-trunc.ll2020-07-07 12:21 9.6K 
[ ]calling-conv-sext-zext.ll2020-07-07 12:21 9.4K 
[ ]float-fcmp.ll2020-07-07 12:21 8.8K 
[ ]callee-saved-gprs.ll2020-07-07 12:21 8.7K 
[ ]urem-lkk.ll2020-07-07 12:21 8.7K 
[ ]calling-conv-ilp32f-ilp32d-common.ll2020-07-07 12:21 8.6K 
[ ]double-mem.ll2020-07-07 12:21 8.1K 
[ ]shifts.ll2020-07-07 12:21 8.1K 
[ ]calls.ll2020-07-07 12:21 7.9K 
[ ]callee-saved-fpr32s.ll2020-07-07 12:21 7.9K 
[ ]frame-info.ll2020-07-07 12:21 7.9K 
[ ]mul.ll2020-07-07 12:21 7.6K 
[ ]double-convert.ll2020-07-07 12:21 7.5K 
[ ]reserved-regs.ll2020-07-07 12:21 7.4K 
[ ]inline-asm.ll2020-07-07 12:21 7.4K 
[ ]remat.ll2020-07-07 12:21 7.1K 
[ ]alu16.ll2020-07-07 12:21 7.0K 
[ ]calling-conv-lp64.ll2020-07-07 12:21 6.9K 
[ ]select-optimize-multiple.mir2020-07-07 12:21 6.9K 
[ ]calling-conv-ilp32.ll2020-07-07 12:21 6.8K 
[ ]large-stack.ll2020-07-07 12:21 6.7K 
[ ]alu8.ll2020-07-07 12:21 6.5K 
[ ]tls-models.ll2020-07-07 12:21 6.3K 
[ ]imm.ll2020-07-07 12:21 6.2K 
[ ]float-mem.ll2020-07-07 12:21 6.2K 
[ ]alu32.ll2020-07-07 12:21 6.1K 
[ ]tail-calls.ll2020-07-07 12:21 6.0K 
[ ]callee-saved-fpr64s.ll2020-07-07 12:21 6.0K 
[ ]mem64.ll2020-07-07 12:21 5.7K 
[ ]hoist-global-addr-base.ll2020-07-07 12:21 5.6K 
[ ]float-convert.ll2020-07-07 12:21 5.2K 
[ ]rv64f-float-convert.ll2020-07-07 12:21 5.1K 
[ ]codemodel-lowering.ll2020-07-07 12:21 5.1K 
[ ]mem.ll2020-07-07 12:21 5.0K 
[ ]double-calling-conv.ll2020-07-07 12:21 4.8K 
[ ]compress.ll2020-07-07 12:21 4.8K 
[ ]umulo-128-legalisation-lowering.ll2020-07-07 12:21 4.3K 
[ ]double-bitmanip-dagcombines.ll2020-07-07 12:21 4.3K 
[ ]frameaddr-returnaddr.ll2020-07-07 12:21 4.3K 
[ ]split-offsets.ll2020-07-07 12:21 4.1K 
[ ]fp16-promote.ll2020-07-07 12:21 4.0K 
[ ]add-before-shl.ll2020-07-07 12:21 3.7K 
[ ]float-bitmanip-dagcombines.ll2020-07-07 12:21 3.6K 
[ ]machineoutliner.mir2020-07-07 12:21 3.6K 
[ ]i32-icmp.ll2020-07-07 12:21 3.5K 
[ ]rv64d-double-convert.ll2020-07-07 12:21 3.5K 
[ ]copysign-casts.ll2020-07-07 12:21 3.4K 
[ ]setcc-logic.ll2020-07-07 12:21 3.4K 
[ ]target-abi-invalid.ll2020-07-07 12:21 3.3K 
[ ]exception-pointer-register.ll2020-07-07 12:21 3.2K 
[ ]alloca.ll2020-07-07 12:21 3.1K 
[ ]fp128.ll2020-07-07 12:21 3.0K 
[ ]rv64i-w-insts-legalization.ll2020-07-07 12:21 3.0K 
[ ]select-cc.ll2020-07-07 12:21 2.9K 
[ ]branch.ll2020-07-07 12:21 2.9K 
[ ]mir-target-flags.ll2020-07-07 12:21 2.9K 
[ ]shrinkwrap.ll2020-07-07 12:21 2.9K 
[ ]calling-conv-rv32f-ilp32.ll2020-07-07 12:21 2.7K 
[ ]pic-models.ll2020-07-07 12:21 2.7K 
[ ]dwarf-eh.ll2020-07-07 12:21 2.5K 
[ ]rv32i-rv64i-float-double.ll2020-07-07 12:21 2.5K 
[ ]interrupt-attr-callee.ll2020-07-07 12:21 2.5K 
[ ]fastcc-int.ll2020-07-07 12:21 2.4K 
[ ]zext-with-load-is-free.ll2020-07-07 12:21 2.3K 
[ ]inline-asm-clobbers.ll2020-07-07 12:21 2.3K 
[ ]inline-asm-d-constraint-f.ll2020-07-07 12:21 2.3K 
[ ]legalize-fneg.ll2020-07-07 12:21 2.3K 
[ ]analyze-branch.ll2020-07-07 12:21 2.2K 
[ ]fastcc-float.ll2020-07-07 12:21 2.2K 
[ ]stack-realignment-with-variable-sized-objects.ll2020-07-07 12:21 2.2K 
[ ]arith-with-overflow.ll2020-07-07 12:21 2.2K 
[ ]rv64i-complex-float.ll2020-07-07 12:21 2.2K 
[ ]double-stack-spill-restore.ll2020-07-07 12:21 2.2K 
[ ]rem.ll2020-07-07 12:21 2.1K 
[ ]calling-conv-lp64-lp64f-common.ll2020-07-07 12:21 2.1K 
[ ]double-imm.ll2020-07-07 12:21 2.0K 
[ ]frame.ll2020-07-07 12:21 1.9K 
[ ]reserved-reg-errors.ll2020-07-07 12:21 1.9K 
[ ]inline-asm-f-constraint-f.ll2020-07-07 12:21 1.9K 
[ ]shift-masked-shamt.ll2020-07-07 12:21 1.9K 
[ ]disable-tail-calls.ll2020-07-07 12:21 1.8K 
[ ]fixups-diff.ll2020-07-07 12:21 1.8K 
[ ]target-abi-valid.ll2020-07-07 12:21 1.8K 
[ ]double-previous-failure.ll2020-07-07 12:21 1.7K 
[ ]branch-relaxation.ll2020-07-07 12:21 1.6K 
[ ]lsr-legaladdimm.ll2020-07-07 12:21 1.6K 
[ ]atomic-fence.ll2020-07-07 12:21 1.6K 
[ ]jumptable.ll2020-07-07 12:21 1.5K 
[ ]float-imm.ll2020-07-07 12:21 1.5K 
[ ]addcarry.ll2020-07-07 12:21 1.5K 
[ ]split-sp-adjust.ll2020-07-07 12:21 1.4K 
[ ]init-array.ll2020-07-07 12:21 1.3K 
[ ]rv64m-w-insts-legalization.ll2020-07-07 12:21 1.3K 
[ ]rv64i-tricky-shifts.ll2020-07-07 12:21 1.3K 
[ ]byval.ll2020-07-07 12:21 1.3K 
[ ]imm-cse.ll2020-07-07 12:21 1.2K 
[ ]rv64-large-stack.ll2020-07-07 12:21 1.1K 
[ ]disjoint.ll2020-07-07 12:21 1.1K 
[ ]atomic-cmpxchg-flag.ll2020-07-07 12:21 1.1K 
[ ]inline-asm-invalid.ll2020-07-07 12:21 1.1K 
[ ]indirectbr.ll2020-07-07 12:21 1.1K 
[ ]get-register-reserve.ll2020-07-07 12:21 1.1K 
[ ]rotl-rotr.ll2020-07-07 12:21 1.0K 
[ ]get-setcc-result-type.ll2020-07-07 12:21 1.0K 
[ ]get-register-noreserve.ll2020-07-07 12:21 965  
[ ]module-target-abi2.ll2020-07-07 12:21 931  
[ ]blockaddress.ll2020-07-07 12:21 920  
[ ]readcyclecounter.ll2020-07-07 12:21 914  
[ ]bare-select.ll2020-07-07 12:21 905  
[ ]wide-mem.ll2020-07-07 12:21 866  
[ ]addc-adde-sube-subc.ll2020-07-07 12:21 855  
[ ]module-target-abi.ll2020-07-07 12:21 805  
[ ]fixups-relax-diff.ll2020-07-07 12:21 775  
[ ]subtarget-features-std-ext.ll2020-07-07 12:21 738  
[ ]musttail-call.ll2020-07-07 12:21 716  
[ ]pr40333.ll2020-07-07 12:21 700  
[ ]flt-rounds.ll2020-07-07 12:21 628  
[ ]prefetch.ll2020-07-07 12:21 597  
[ ]sdata-local-sym.ll2020-07-07 12:21 535  
[ ]double-frem.ll2020-07-07 12:21 526  
[ ]float-frem.ll2020-07-07 12:21 522  
[ ]sdata-limit-4.ll2020-07-07 12:21 516  
[ ]sdata-limit-8.ll2020-07-07 12:21 506  
[ ]sdata-limit-0.ll2020-07-07 12:21 504  
[ ]option-norvc.ll2020-07-07 12:21 485  
[ ]option-rvc.ll2020-07-07 12:21 483  
[ ]option-relax.ll2020-07-07 12:21 441  
[ ]option-norelax.ll2020-07-07 12:21 441  
[ ]compress-inline-asm.ll2020-07-07 12:21 425  
[ ]inline-asm-i-constraint-i1.ll2020-07-07 12:21 385  
[ ]interrupt-attr-ret-error.ll2020-07-07 12:21 335  
[ ]interrupt-attr-args-error.ll2020-07-07 12:21 333  
[ ]interrupt-attr-invalid.ll2020-07-07 12:21 318  
[ ]align.ll2020-07-07 12:21 318  
[ ]get-register-invalid.ll2020-07-07 12:21 299  
[ ]verify-instr.mir2020-07-07 12:21 254  
[ ]rv32e.ll2020-07-07 12:21 175  
[ ]mattr-invalid-combination.ll2020-07-07 12:21 162  
[ ]lit.local.cfg2020-07-07 12:21 69  
[DIR]intrinsics/2020-07-07 12:21 -  
[DIR]GlobalISel/2020-07-07 12:21 -