Index of /llvm-8.0.1/test/CodeGen/Hexagon

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[DIR]autohvx/2019-07-19 10:14 -  
[DIR]intrinsics/2019-07-19 10:14 -  
[DIR]loop-idiom/2019-07-19 10:14 -  
[DIR]vect/2019-07-19 10:14 -  
[ ]lit.local.cfg2014-06-09 18:42 72  
[ ]isel-i1arg-crash.ll2017-03-01 12:30 109  
[ ]inline-asm-filetype-null.ll2018-11-01 11:41 136  
[ ]generic-cpu.ll2018-06-26 14:44 142  
[ ]duplex.ll2017-11-30 11:12 147  
[ ]trap-unreachable.ll2018-08-09 14:03 150  
[ ]predicate-copy.ll2018-10-19 13:31 184  
[ ]no-falign-function-for-size.ll2018-03-12 10:01 206  
[ ]checktabs.ll2015-06-18 16:43 225  
[ ]maxd.ll2015-06-17 16:29 226  
[ ]maxw.ll2015-06-17 16:29 226  
[ ]mind.ll2015-06-17 16:29 226  
[ ]minw.ll2015-06-17 16:29 226  
[ ]maxud.ll2015-06-17 16:29 227  
[ ]maxuw.ll2015-06-17 16:29 227  
[ ]minud.ll2015-06-17 16:29 227  
[ ]minuw.ll2015-06-17 16:29 227  
[ ]store-imm-byte.ll2018-03-12 10:01 236  
[ ]bit-skip-byval.ll2017-02-10 10:33 238  
[ ]store-imm-halword.ll2018-03-12 10:01 239  
[ ]store-imm-word.ll2018-03-12 10:01 239  
[ ]vsplat-isel.ll2016-05-12 13:21 239  
[ ]sdata-explicit-section.ll2018-11-09 12:31 242  
[ ]expand-condsets-basic.ll2015-03-31 09:35 244  
[ ]vararg-formal.ll2018-02-15 10:47 245  
[ ]simple_addend.ll2015-10-19 13:46 246  
[ ]readcyclecounter.ll2017-02-22 17:28 250  
[ ]lower-i1.ll2018-03-12 10:01 253  
[ ]indirect-br.ll2018-08-02 18:17 263  
[ ]relax.ll2018-05-14 15:46 263  
[ ]sdata-opaque-type.ll2018-03-12 10:01 265  
[ ]lcomm.ll2018-03-12 10:01 277  
[ ]dont_rotate_pregs_at_O2.ll2018-08-02 18:17 284  
[ ]not-op.ll2018-03-12 10:01 293  
[ ]namedreg.ll2018-09-07 09:36 294  
[ ]sdata-array.ll2017-10-20 15:33 295  
[ ]add_int_double.ll2018-03-12 10:01 297  
[ ]combine_lh.ll2018-03-12 10:01 298  
[ ]dualstore.ll2015-06-05 12:00 298  
[ ]tstbit.ll2018-03-12 10:01 298  
[ ]expand-condsets-pred-undef2.ll2018-11-18 11:50 309  
[ ]newvaluestore.ll2016-05-26 15:44 311  
[ ]minu-zext-8.ll2015-06-17 16:29 313  
[ ]mux-kill1.mir2018-01-31 17:04 313  
[ ]extlow.ll2018-03-12 10:01 315  
[ ]duplex-addi-global-imm.mir2018-01-31 17:04 316  
[ ]bug9963.ll2018-03-12 10:01 318  
[ ]expand-vselect-kill.mir2018-06-20 15:22 318  
[ ]rdf-ehlabel-live.mir2018-01-31 17:04 319  
[ ]compound.ll2017-02-17 17:14 325  
[ ]minu-zext-16.ll2015-06-17 16:29 327  
[ ]storerd-io-over-rr.ll2016-08-02 14:50 330  
[ ]addaddi.ll2017-10-23 15:07 334  
[ ]neg.ll2018-06-05 15:52 338  
[ ]pic-local.ll2017-02-10 10:33 338  
[ ]vector-ext-load.ll2016-09-08 13:42 339  
[ ]bit-extractu-half.ll2016-01-14 16:59 341  
[ ]dccleana.ll2018-03-12 10:01 341  
[ ]ret-struct-by-val.ll2017-02-10 10:33 344  
[ ]simpletailcall.ll2018-10-19 13:31 349  
[ ]args.ll2018-03-06 14:15 350  
[ ]expand-wselect.mir2018-12-07 17:00 352  
[ ]calling-conv-2.ll2018-03-06 14:15 368  
[ ]struct_args.ll2016-07-26 14:30 369  
[ ]eh_return-r30.ll2018-03-12 10:01 375  
[ ]stack-alloca1.ll2017-02-10 10:33 375  
[ ]invalid-dotnew-attempt.mir2018-01-31 17:04 377  
[ ]initial-exec.ll2018-03-12 10:01 382  
[ ]extract_0bits.ll2018-03-12 10:01 383  
[ ]store-widen-negv.ll2015-10-16 15:43 384  
[ ]extractu_0bits.ll2018-03-12 10:01 385  
[ ]isel-vacopy.ll2018-03-02 13:35 385  
[ ]struct_args_large.ll2016-02-04 11:21 388  
[ ]constp-vsplat.ll2018-03-06 14:15 389  
[ ]macint.ll2018-10-19 13:31 389  
[ ]float-const64-G0.ll2018-03-12 10:01 393  
[ ]sdiv-minsigned.ll2018-06-28 13:33 397  
[ ]check-dot-new.ll2018-03-12 10:01 399  
[ ]storerinewabs.ll2016-04-19 16:20 399  
[ ]vect-any_extend.ll2018-03-12 10:01 400  
[ ]constp-rewrite-branches.ll2018-03-06 14:15 406  
[ ]newvaluejump-solo.mir2018-01-31 17:04 406  
[ ]combine-imm-ext.ll2018-03-12 10:01 407  
[ ]rdf-copy-renamable-reserved.mir2018-01-31 17:04 408  
[ ]constp-rseq.ll2016-07-28 16:01 409  
[ ]inline-asm-error.ll2018-03-12 10:01 411  
[ ]ashift-left-right.ll2015-06-13 17:46 416  
[ ]combine-imm-ext2.ll2018-03-12 10:01 416  
[ ]hello-world-v55.ll2018-03-12 10:01 417  
[ ]hello-world-v60.ll2018-03-12 10:01 417  
[ ]muxii-crash.ll2018-03-12 10:01 418  
[ ]inline-asm-i1.ll2016-08-19 15:36 424  
[ ]inline-asm-a.ll2017-07-21 13:51 425  
[ ]v6vec-vmemcur-prob.mir2018-03-12 10:01 427  
[ ]mpysin-imm.ll2018-03-12 10:01 428  
[ ]early-if-phi-i1.ll2017-03-21 12:59 430  
[ ]packetize-dccleana.mir2018-06-19 13:26 432  
[ ]pred-absolute-store.ll2018-02-21 11:37 434  
[ ]addrmode-globoff.mir2018-01-31 17:04 436  
[ ]common-global-addr.ll2018-03-12 10:01 436  
[ ]sdata-basic.ll2016-04-21 14:56 436  
[ ]newvaluejump-float.mir2018-02-06 14:08 437  
[ ]isel-vlsr-v2i16.ll2018-12-14 17:33 440  
[ ]opt-fabs.ll2017-02-10 10:33 440  
[ ]sfmin_dce.ll2018-03-12 10:01 440  
[ ]mux-kill2.mir2018-01-31 17:04 441  
[ ]align_Os.ll2018-03-12 10:01 443  
[ ]getBlockAddress.ll2018-03-12 10:01 444  
[ ]dfp.ll2018-12-05 16:01 445  
[ ]tailcall_fastcc_ccc.ll2016-08-19 11:02 445  
[ ]isel-op-zext-i1.ll2017-03-09 11:29 446  
[ ]packetize-tailcall-arg.ll2016-07-14 15:30 447  
[ ]misaligned-access.ll2018-10-19 13:31 456  
[ ]stack-align1.ll2017-02-10 10:33 457  
[ ]const64.ll2016-01-15 09:08 462  
[ ]static.ll2017-02-06 18:18 464  
[ ]retval-redundant-copy.ll2018-03-26 13:53 467  
[ ]bit-addr-align.mir2018-02-20 09:29 469  
[ ]cext.ll2018-03-06 14:07 469  
[ ]bug9049.ll2018-03-12 10:01 470  
[ ]expand-condsets-imm.mir2018-01-31 17:04 471  
[ ]sdata-expand-const.ll2018-03-12 10:01 472  
[ ]callr-dep-edge.ll2018-03-06 14:15 474  
[ ]fsel.ll2017-02-10 10:33 474  
[ ]circ-load-isel.ll2016-05-13 14:48 475  
[ ]combine.ll2018-03-06 14:15 478  
[ ]cexti16.ll2018-03-06 14:07 480  
[ ]inline-asm-vecpred128.ll2017-10-18 14:07 481  
[ ]M4_mpyri_addi_global.ll2018-03-12 10:01 485  
[ ]addrmode-rr-to-io.mir2018-01-31 17:04 485  
[ ]undef-ret.ll2018-03-12 10:01 487  
[ ]feature-memops.ll2018-05-14 16:09 490  
[ ]newvaluejump-kill2.mir2018-01-31 17:04 491  
[ ]ctor.ll2014-11-03 09:56 493  
[ ]hwloop-ice.ll2018-03-12 10:01 495  
[ ]constp-clb.ll2018-03-06 14:15 496  
[ ]isel-exti1.ll2017-02-28 17:37 500  
[ ]sdr-global.mir2018-05-04 11:04 500  
[ ]store-widen-negv2.ll2015-10-16 15:43 501  
[ ]tcm-zext.ll2018-03-12 10:01 502  
[ ]mnaci_v66.ll2018-12-05 16:01 503  
[ ]union-1.ll2018-10-19 13:31 504  
[ ]csr_stub_calls_dwarf_frame_info.ll2018-03-12 10:01 508  
[ ]sdata-load-size.ll2018-11-02 10:17 512  
[ ]bit-bitsplit.ll2017-10-18 14:07 514  
[ ]vaddh.ll2018-10-19 13:31 514  
[ ]absimm.ll2018-03-06 14:07 518  
[ ]callR_noreturn.ll2018-08-02 18:17 527  
[ ]memop-bit18.ll2018-03-12 10:01 529  
[ ]sdr-basic.ll2015-10-16 16:38 532  
[ ]stack-alloca2.ll2017-02-10 10:33 536  
[ ]fusedandshift.ll2017-02-28 18:27 542  
[ ]unreachable-mbb-phi-subreg.mir2018-01-31 17:04 543  
[ ]common-gep-inbounds.ll2018-01-24 12:48 545  
[ ]constp-andir-global.mir2018-02-23 15:33 547  
[ ]tail-call-trunc.ll2013-08-06 05:12 551  
[ ]hwloop-ph-deadcode.ll2015-05-14 13:31 554  
[ ]global-const-gep.ll2018-03-12 10:01 555  
[ ]inline-asm-bad-constraint.ll2017-10-20 16:24 556  
[ ]addrmode-keepdeadphis.mir2018-01-31 17:04 557  
[ ]postinc-baseoffset.mir2018-01-31 17:04 559  
[ ]glob-align-volatile.ll2018-03-12 10:01 563  
[ ]cext-valid-packet1.ll2017-02-10 10:33 564  
[ ]build-vector-v4i8-zext.ll2017-11-28 14:13 567  
[ ]mpy.ll2018-10-19 13:31 574  
[ ]call-ret-i1.ll2017-10-23 15:35 576  
[ ]optimize-mux.ll2018-03-23 14:43 576  
[ ]packetize-call-r29.ll2018-03-12 10:01 576  
[ ]mulh.ll2017-11-22 15:43 581  
[ ]prefetch-intr.ll2018-03-12 10:01 583  
[ ]fmadd.ll2018-03-12 10:01 585  
[ ]prefetch-shuffler-ice.ll2018-03-12 10:01 586  
[ ]formal-args-i1.ll2018-03-23 14:43 587  
[ ]avoidVectorLowering.ll2018-03-12 10:01 588  
[ ]dadd.ll2017-07-05 09:08 589  
[ ]v6vec_zero.ll2018-03-12 10:01 592  
[ ]dmul.ll2017-07-05 09:08 593  
[ ]dsub.ll2017-07-05 09:08 593  
[ ]mulhs.ll2016-08-08 15:24 593  
[ ]fadd.ll2017-07-05 09:08 595  
[ ]local-exec.ll2018-03-12 10:01 598  
[ ]fsub.ll2017-07-05 09:08 600  
[ ]rotl-i64.ll2018-08-02 18:17 603  
[ ]pic-simple.ll2017-02-10 10:33 605  
[ ]store-widen.ll2015-10-16 15:43 608  
[ ]hwloop-wrap.ll2015-05-14 10:15 611  
[ ]inline-asm-qv.ll2017-11-22 15:43 613  
[ ]bank-conflict-load.mir2018-01-31 17:04 615  
[ ]fmul.ll2017-07-05 09:08 615  
[ ]pic-static.ll2017-02-10 10:33 615  
[ ]bit-validate-reg.ll2017-02-28 18:27 620  
[ ]base-offset-addr.ll2015-06-13 17:46 621  
[ ]tls_gd.ll2018-03-12 10:01 623  
[ ]constp-ctb.ll2018-03-06 14:15 624  
[ ]maddsubu.ll2018-03-12 10:01 628  
[ ]inline-asm-clobber-lr.ll2018-03-12 10:01 631  
[ ]expand-condsets-pred-undef.ll2016-04-22 12:47 633  
[ ]M4_mpyrr_addi_global.ll2018-03-12 10:01 634  
[ ]split-muxii.ll2018-03-23 14:43 634  
[ ]packetize-nvstore.mir2018-09-04 17:07 635  
[ ]addsubcarry.ll2018-06-01 10:00 644  
[ ]hexagon-cond-jumpr31.ll2018-03-20 15:35 648  
[ ]mux-undef.ll2018-08-02 18:17 648  
[ ]stack-align2.ll2017-02-10 10:33 654  
[ ]dealloc_return.ll2018-03-12 10:01 658  
[ ]circ_ldw.ll2018-03-06 14:15 659  
[ ]asr-rnd64.ll2018-03-12 10:01 664  
[ ]vect-zero_extend.ll2018-03-12 10:01 664  
[ ]build-vector-shuffle.ll2018-08-02 18:17 671  
[ ]expand-condsets-impuse2.mir2018-07-10 10:49 675  
[ ]swp-regseq.ll2018-03-12 10:01 678  
[ ]isel-setcc-i1.ll2018-08-02 18:17 679  
[ ]add-use.ll2018-03-12 10:01 680  
[ ]testbits.ll2018-03-12 10:01 680  
[ ]phi-elim.ll2018-03-12 10:01 681  
[ ]pred-simp.ll2018-03-12 10:01 681  
[ ]opt-fneg.ll2017-02-10 10:33 683  
[ ]subh.ll2018-03-12 10:01 686  
[ ]ifcvt-diamond-ret.mir2018-04-19 13:26 688  
[ ]predicate-rcmp.ll2017-02-10 10:33 691  
[ ]subh-shifted.ll2018-03-12 10:01 691  
[ ]vect-vd0.ll2018-03-12 10:01 691  
[ ]newvaluestore2.ll2018-03-12 10:01 692  
[ ]peephole-kill-flags.ll2018-08-02 18:17 693  
[ ]float.ll2018-10-19 13:31 695  
[ ]floatconvert-ieee-rnd-near.ll2018-10-19 13:31 695  
[ ]hidden-relocation.ll2018-03-12 10:01 695  
[ ]tail-dup-subreg-abort.ll2015-10-20 22:40 700  
[ ]vextract-basic.mir2018-01-31 17:04 713  
[ ]hwloop3.ll2015-05-08 16:18 715  
[ ]late-pred.ll2018-06-11 14:45 719  
[ ]expand-condsets-undef.ll2015-03-31 09:35 720  
[ ]split-const32-const64.ll2017-11-22 15:43 725  
[ ]call-long1.ll2018-03-12 10:01 727  
[ ]addh.ll2017-02-10 10:33 729  
[ ]ifcvt-simple-bprob.ll2017-03-06 14:12 732  
[ ]addh-shifted.ll2017-02-10 10:33 734  
[ ]tls_static.ll2017-10-20 15:33 735  
[ ]expand-condsets-same-inputs.mir2018-01-31 17:04 740  
[ ]double.ll2018-10-19 13:31 743  
[ ]newvaluejump2.ll2017-11-22 15:43 743  
[ ]cmpbeq.ll2018-03-12 10:01 744  
[ ]store-widen-aliased-load.ll2015-10-16 15:43 747  
[ ]asr-rnd.ll2018-03-12 10:01 753  
[ ]loadi1-v4-G0.ll2015-06-17 16:29 753  
[ ]bug31839.ll2018-03-12 10:01 755  
[ ]memset-inline.ll2018-03-12 10:01 757  
[ ]loadi1-v4.ll2015-06-17 16:29 761  
[ ]mipi-double-small.ll2018-03-12 10:01 762  
[ ]v62-inlasm4.ll2018-03-12 10:01 764  
[ ]dag-combine-select-or0.ll2018-03-12 10:01 766  
[ ]loadi1-G0.ll2015-06-17 16:29 769  
[ ]hwloop-swap.ll2018-03-12 10:01 772  
[ ]loadi1.ll2015-06-17 16:29 777  
[ ]early-if-low8.mir2018-02-20 13:19 778  
[ ]hwloop-subreg.ll2018-04-06 13:51 783  
[ ]noreturn-notail.ll2018-03-12 10:01 784  
[ ]bss-local.ll2018-03-12 10:01 788  
[ ]vsplat-ext.ll2018-03-12 10:01 793  
[ ]call-v4.ll2018-03-12 10:01 795  
[ ]opt-sext-intrinsics.ll2018-03-12 10:01 801  
[ ]tfr-to-combine.ll2017-10-20 15:33 802  
[ ]maxh.ll2015-06-17 16:29 803  
[ ]ignore-terminal-mbb.ll2018-08-02 18:17 805  
[ ]v6vect-vmem1.ll2018-03-12 10:01 807  
[ ]memops3.ll2018-03-06 14:07 811  
[ ]noFalignAfterCallAtO2.ll2018-03-12 10:01 813  
[ ]rdf-reset-kills.ll2016-04-20 10:33 817  
[ ]sdr-shr32.ll2015-10-16 16:38 817  
[ ]swp-order-deps5.ll2018-03-26 12:23 817  
[ ]packetize-nvj-no-prune.mir2018-01-31 17:04 818  
[ ]v6-inlasm4.ll2018-03-12 10:01 818  
[ ]nv_store_vec.ll2018-03-12 10:01 819  
[ ]hwloop-with-return-call.ll2018-03-12 10:01 826  
[ ]ntstbit.ll2018-03-12 10:01 829  
[ ]bit-extract-off.ll2018-08-02 18:17 831  
[ ]target-flag-ext.mir2018-01-31 17:04 831  
[ ]swp-order-deps6.ll2018-03-12 10:01 832  
[ ]noreturn-noepilog.ll2018-03-22 16:06 835  
[ ]memops2.ll2018-03-06 14:07 837  
[ ]hwloop-const.ll2018-10-19 13:31 838  
[ ]expand-condsets-phys-reg.mir2018-05-04 09:59 839  
[ ]packetize-volatiles.ll2018-03-12 10:01 845  
[ ]addh-sext-trunc.ll2017-02-10 10:33 846  
[ ]cmp-to-genreg.ll2018-03-06 14:07 849  
[ ]tfr-mux-nvj.ll2018-08-02 18:17 853  
[ ]combine_ir.ll2018-03-06 14:15 856  
[ ]swp-rename.ll2018-03-20 15:35 857  
[ ]v60_Q6_P_rol_PI.ll2018-03-12 10:01 862  
[ ]cext-valid-packet2.ll2018-03-06 14:15 864  
[ ]cext-opt-shifted-range.mir2018-01-31 17:04 872  
[ ]swp-phi-order.ll2018-03-12 10:01 875  
[ ]vmemu-128.ll2018-03-12 10:01 875  
[ ]convertsptoint.ll2017-07-05 09:08 877  
[ ]bug18491-optsize.ll2018-03-12 10:01 878  
[ ]float-bitcast.ll2018-03-12 10:01 883  
[ ]addasl-address.ll2018-03-12 10:01 888  
[ ]cmpb-dec-imm.ll2017-10-13 11:43 893  
[ ]packetize_cond_inst.ll2018-10-19 13:31 893  
[ ]setmemrefs.ll2018-03-12 10:01 893  
[ ]store_abs.ll2018-03-12 10:01 893  
[ ]packetize-update-offset.mir2018-03-30 15:46 894  
[ ]base-offset-stv4.ll2018-03-12 10:01 897  
[ ]opt-spill-volatile.ll2017-04-10 16:18 905  
[ ]pred-gp.ll2018-10-19 13:31 905  
[ ]branchfolder-keep-impdef.ll2018-03-06 14:15 911  
[ ]convertdptoint.ll2017-07-05 09:08 911  
[ ]mlong-calls.ll2018-03-20 15:35 916  
[ ]convertsptoll.ll2017-07-05 09:08 918  
[ ]newvaluejump-c4.mir2018-01-31 17:04 919  
[ ]swp-order-deps3.ll2018-03-12 10:01 919  
[ ]struct_copy_sched_r16.ll2018-03-12 10:01 920  
[ ]select-instr-align.ll2018-03-07 12:27 922  
[ ]swp-order-prec.ll2018-03-12 10:01 923  
[ ]isel-combine-half.ll2017-11-22 15:55 924  
[ ]two-crash.ll2017-02-10 10:33 926  
[ ]bit-bitsplit-at.ll2018-08-02 18:17 932  
[ ]pred-instrs.ll2018-10-19 13:31 934  
[ ]vadd1.ll2018-03-12 10:01 935  
[ ]newvaluejump.ll2018-10-19 13:31 937  
[ ]zextloadi1.ll2017-10-13 15:02 939  
[ ]ifcvt-common-kill.mir2018-01-31 17:04 940  
[ ]postinc-store.ll2018-10-19 13:31 942  
[ ]convertdptoll.ll2017-07-05 09:08 943  
[ ]constp-physreg.ll2016-07-28 16:01 946  
[ ]swp-fix-last-use.ll2018-03-12 10:01 947  
[ ]vgather-packetize.mir2018-08-17 10:24 951  
[ ]postinc-load.ll2018-10-19 13:31 953  
[ ]vcombine_subreg.ll2018-03-12 10:01 958  
[ ]v6vassignp.ll2018-03-12 10:01 959  
[ ]inline-asm-hexagon.ll2016-07-26 13:31 962  
[ ]cext-opt-range-offset.mir2018-01-31 17:04 963  
[ ]deflate.ll2018-03-12 10:01 964  
[ ]mux-kill3.mir2018-01-31 17:04 1.0K 
[ ]sfmpyacc_scale.ll2018-03-12 10:01 1.0K 
[ ]regalloc-liveout-undef.mir2018-01-31 17:04 1.0K 
[ ]sffms.ll2016-08-19 09:34 1.0K 
[ ]post-ra-kill-update.mir2018-01-31 17:04 1.0K 
[ ]hwloop-range.ll2015-04-27 10:16 1.0K 
[ ]tail-call-mem-intrinsics.ll2018-01-19 12:13 1.0K 
[ ]block-address.ll2018-03-12 10:01 1.0K 
[ ]swp-vmult.ll2018-04-10 18:07 1.0K 
[ ]v6-inlasm2.ll2018-03-12 10:01 1.0K 
[ ]no_struct_element.ll2018-03-12 10:01 1.0K 
[ ]vasrh.select.ll2018-03-12 10:01 1.0K 
[ ]store1.ll2018-03-12 10:01 1.0K 
[ ]jump-table-g0.ll2018-03-12 10:01 1.0K 
[ ]swp-vsum.ll2018-03-26 11:32 1.0K 
[ ]usr-ovf-dep.ll2015-06-18 16:43 1.0K 
[ ]hvx-vzero.ll2018-03-12 10:01 1.0K 
[ ]store-constant.ll2018-03-12 10:01 1.0K 
[ ]memops1.ll2018-03-06 14:07 1.0K 
[ ]hvx-double-vzero.ll2018-03-12 10:01 1.0K 
[ ]hvx-loopidiom-memcpy.ll2018-03-12 10:01 1.0K 
[ ]tls_pic.ll2017-10-20 15:33 1.0K 
[ ]ifcvt-impuse-livein.mir2018-01-31 17:04 1.0K 
[ ]livephysregs-lane-masks.mir2018-01-31 17:04 1.0K 
[ ]gp-rel.ll2018-10-19 13:31 1.0K 
[ ]shrink-frame-basic.ll2015-04-23 12:05 1.0K 
[ ]v6vec-vmemu2.ll2018-03-19 15:03 1.0K 
[ ]expand-condsets-def-undef.mir2018-01-31 17:04 1.0K 
[ ]fminmax.ll2017-10-18 14:07 1.0K 
[ ]fcmp.ll2015-02-27 16:17 1.0K 
[ ]cext-opt-numops.mir2018-01-31 17:04 1.0K 
[ ]hvx-nontemporal.ll2017-10-18 14:07 1.0K 
[ ]swp-subreg.ll2018-03-12 10:01 1.0K 
[ ]livephysregs-add-pristines.mir2018-01-31 17:04 1.1K 
[ ]packetize-load-store-aliasing.mir2018-01-31 17:04 1.1K 
[ ]peephole-op-swap.ll2016-04-19 17:36 1.1K 
[ ]V60-VDblNew.ll2018-03-12 10:01 1.1K 
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[ ]hwloop-wrap2.ll2015-05-14 10:15 2.3K 
[ ]store-AbsSet.ll2018-03-12 10:01 2.3K 
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[ ]v5_insns.ll2018-03-12 10:01 2.5K 
[ ]aggressive_licm.ll2018-03-12 10:01 2.5K 
[ ]rdf-phi-shadows.ll2016-09-07 16:37 2.5K 
[ ]cfi-late.ll2019-01-15 11:18 2.5K 
[ ]rdf-extra-livein.ll2018-08-02 18:17 2.5K 
[ ]tail-dup-subreg-map.ll2018-08-02 18:17 2.5K 
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[ ]vrcmpys.ll2018-03-12 10:01 2.5K 
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[ ]store-imm-amode.ll2017-10-20 15:33 2.5K 
[ ]verify-liveness-at-def.mir2018-09-20 02:59 2.5K 
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[ ]bug17386.ll2018-03-12 10:01 2.6K 
[ ]dealloc-store.ll2018-08-02 18:17 2.6K 
[ ]mul64-sext.ll2018-02-27 17:44 2.6K 
[ ]bugAsmHWloop.ll2015-06-18 16:43 2.6K 
[ ]swp-kernel-last-use.ll2018-03-12 10:01 2.7K 
[ ]v60-halide-vcombinei8.ll2018-08-02 18:17 2.7K 
[ ]early-if-vecpi.ll2017-10-18 14:07 2.7K 
[ ]BranchPredict.ll2018-08-02 18:17 2.7K 
[ ]cmp_pred.ll2018-03-23 14:43 2.7K 
[ ]cmp_pred_reg.ll2018-03-23 14:43 2.7K 
[ ]noreturn-stack-elim.ll2018-11-09 13:16 2.7K 
[ ]Atomics.ll2016-06-22 12:07 2.7K 
[ ]swp-order-deps4.ll2018-03-12 10:01 2.7K 
[ ]trunc-mpy.ll2018-03-12 10:01 2.8K 
[ ]swp-epilog-phi2.ll2018-08-02 18:17 2.8K 
[ ]v6vec_inc1.ll2018-03-19 17:05 2.8K 
[ ]bug17276.ll2018-03-12 10:01 2.8K 
[ ]swp-stages5.ll2017-02-10 10:33 2.8K 
[ ]postinc-float.ll2018-05-18 14:14 2.8K 
[ ]bitmanip.ll2017-02-23 10:02 2.9K 
[ ]v6vect-vsplat.ll2018-03-12 10:01 2.9K 
[ ]v60small.ll2017-10-18 14:07 2.9K 
[ ]swp-epilog-phi6.ll2018-09-19 14:52 2.9K 
[ ]swp-matmul-bitext.ll2017-05-03 16:10 2.9K 
[ ]hwloop4.ll2017-02-10 10:33 2.9K 
[ ]loop-rotate-bug.ll2018-03-12 10:01 3.0K 
[ ]misaligned_double_vector_store_not_fast.ll2017-10-18 14:07 3.0K 
[ ]bug18008.ll2018-03-12 10:01 3.0K 
[ ]csr-func-usedef.ll2016-04-25 13:49 3.0K 
[ ]loop-rotate-liveins.ll2018-03-12 10:01 3.0K 
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[ ]swp-stages.ll2018-03-12 10:01 3.0K 
[ ]jump-table-isel.ll2018-03-12 10:01 3.1K 
[ ]upper-mpy.ll2018-03-12 10:01 3.1K 
[ ]eh_save_restore.ll2018-03-12 10:01 3.1K 
[ ]i128-bitop.ll2018-03-12 10:01 3.1K 
[ ]loop_correctness.ll2018-03-12 10:01 3.1K 
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[ ]store-imm-stack-object.ll2018-01-19 12:13 3.1K 
[ ]sub-add.ll2018-03-12 10:01 3.1K 
[ ]swp-epilog-reuse.ll2016-07-29 12:44 3.1K 
[ ]common-gep-icm.ll2015-07-08 15:22 3.1K 
[ ]vassign-to-combine.ll2018-08-02 18:17 3.1K 
[ ]v60-vsel1.ll2017-10-18 14:07 3.1K 
[ ]debug-prologue.ll2018-05-08 22:40 3.1K 
[ ]hwloop-dbg.ll2018-10-19 13:31 3.1K 
[ ]early-if.ll2018-03-06 14:15 3.1K 
[ ]swp-prolog-phi4.ll2016-12-22 13:49 3.2K 
[ ]fpelim-basic.ll2017-06-30 17:21 3.2K 
[ ]invalid-memrefs.ll2018-03-12 10:01 3.2K 
[ ]early-if-merge-loop.ll2017-10-18 14:07 3.2K 
[ ]debug-prologue-loc.ll2018-05-08 22:40 3.2K 
[ ]swp-epilog-reuse3.ll2018-03-12 10:01 3.3K 
[ ]adjust-latency-stackST.ll2018-03-06 14:15 3.3K 
[ ]v60-cur.ll2018-08-02 18:17 3.3K 
[ ]coalesce_tfri.ll2018-03-12 10:01 3.3K 
[ ]fp_latency.ll2018-05-16 18:49 3.3K 
[ ]brev_ld.ll2018-04-03 12:05 3.4K 
[ ]mem-load-circ.ll2018-03-12 10:01 3.4K 
[ ]dead-store-stack.ll2018-03-06 14:15 3.5K 
[ ]swp-stages4.ll2018-03-20 13:03 3.5K 
[ ]pic-regusage.ll2018-03-06 14:07 3.5K 
[ ]Halide_vec_cast_trunc1.ll2018-03-12 10:01 3.6K 
[ ]vcombine128_to_req_seq.ll2018-03-12 10:01 3.6K 
[ ]sdr-reg-profit.ll2018-04-10 18:07 3.6K 
[ ]bug6757-endloop.ll2018-03-12 10:01 3.6K 
[ ]v6-shuffl.ll2018-03-12 10:01 3.7K 
[ ]swp-intreglow8.ll2018-03-12 10:01 3.7K 
[ ]postinc-aggr-dag-cycle.ll2018-03-12 10:01 3.7K 
[ ]mapped_intrinsics.ll2018-03-12 10:01 3.7K 
[ ]bug-allocframe-size.ll2018-03-12 10:01 3.7K 
[ ]circ_st.ll2018-03-06 14:15 3.7K 
[ ]newvaluejump-postinc.ll2018-03-12 10:01 3.7K 
[ ]brev_st.ll2018-03-29 09:52 3.7K 
[ ]v60-vsel2.ll2018-03-12 10:01 3.8K 
[ ]save-regs-thresh.ll2018-03-12 10:01 3.8K 
[ ]bkfir.ll2018-03-12 10:01 3.8K 
[ ]bug-hcp-tied-kill.ll2018-03-12 10:01 3.8K 
[ ]bit-cmp0.mir2018-07-30 10:28 3.8K 
[ ]v60_sort16.ll2018-03-12 10:01 3.8K 
[ ]float-amode.ll2017-02-10 10:33 3.8K 
[ ]swp-epilog-reuse4.ll2018-03-12 10:01 3.9K 
[ ]swp-copytophi-dag.ll2018-10-19 02:20 3.9K 
[ ]reg_seq.ll2018-03-12 10:01 3.9K 
[ ]expand-vstorerw-undef.ll2018-08-02 18:17 3.9K 
[ ]NVJumpCmp.ll2015-12-08 11:28 3.9K 
[ ]cmpb_gtu.ll2018-03-12 10:01 4.0K 
[ ]swp-epilog-numphis.ll2018-03-26 11:32 4.0K 
[ ]swp-epilog-phi10.ll2016-12-22 13:49 4.0K 
[ ]vect_setcc_v2i16.ll2018-03-12 10:01 4.0K 
[ ]rotate.ll2018-12-20 11:39 4.0K 
[ ]hwloop5.ll2017-02-10 10:33 4.0K 
[ ]bit-loop.ll2018-03-06 14:07 4.0K 
[ ]expand-condsets.ll2018-03-12 10:01 4.0K 
[ ]swp-phi-def-use.ll2018-03-12 10:01 4.0K 
[ ]swp-phi-dep1.ll2018-03-12 10:01 4.0K 
[ ]Halide_vec_cast_trunc2.ll2018-03-12 10:01 4.1K 
[ ]cfi_offset2.ll2018-03-12 10:01 4.1K 
[ ]swp-const-tc3.ll2018-03-12 10:01 4.1K 
[ ]split-vecpred.ll2018-03-12 10:01 4.2K 
[ ]v6-inlasm1.ll2018-03-12 10:01 4.2K 
[ ]expand-condsets-extend.ll2016-09-01 09:59 4.2K 
[ ]vec-pred-spill1.ll2018-03-06 14:07 4.3K 
[ ]hasfp-crash2.ll2018-05-08 22:40 4.3K 
[ ]hasfp-crash1.ll2018-05-08 22:40 4.3K 
[ ]opt-addr-mode.ll2017-02-10 10:33 4.4K 
[ ]cmp.ll2017-02-10 10:33 4.5K 
[ ]swp-disable-Os.ll2018-03-12 10:01 4.5K 
[ ]hwloop1.ll2017-02-10 10:33 4.5K 
[ ]twoaddressbug.ll2018-03-12 10:01 4.5K 
[ ]clr_set_toggle.ll2018-10-10 10:15 4.6K 
[ ]packetize-impdef-1.ll2018-08-02 18:17 4.6K 
[ ]hexagon_cfi_offset.ll2018-03-12 10:01 4.6K 
[ ]swp-memrefs-epilog.ll2018-05-18 14:14 4.6K 
[ ]expand-condsets-rm-segment.ll2018-03-06 14:15 4.6K 
[ ]vpack_eo.ll2017-10-18 14:07 4.6K 
[ ]save-kill-csr.ll2018-03-12 10:01 4.6K 
[ ]hexagon_vector_loop_carried_reuse_constant.ll2017-10-18 14:07 4.7K 
[ ]hexagon_vector_loop_carried_reuse.ll2017-10-18 14:07 4.7K 
[ ]reg-scavengebug-3.ll2017-10-18 14:07 4.8K 
[ ]swp-resmii-1.ll2018-03-26 13:53 4.8K 
[ ]memops-stack.ll2017-10-18 14:07 4.9K 
[ ]v60-haar-postinc.ll2018-03-12 10:01 4.9K 
[ ]circ_ld.ll2018-03-06 14:15 5.0K 
[ ]multi-cycle.ll2018-12-03 17:40 5.0K 
[ ]convert-to-dot-old.ll2017-10-18 14:07 5.1K 
[ ]regalloc-block-overlap.ll2018-01-24 12:48 5.3K 
[ ]swp-art-deps-rec.ll2018-10-25 23:15 5.3K 
[ ]rdf-copy-undef.ll2018-03-12 10:01 5.3K 
[ ]swp-bad-sched.ll2018-03-26 13:53 5.4K 
[ ]insert4.ll2017-02-10 10:33 5.4K 
[ ]regp-underflow.ll2018-03-12 10:01 5.5K 
[ ]barrier-flag.ll2018-03-06 14:15 5.5K 
[ ]prob-types.ll2018-03-12 10:01 5.5K 
[ ]intrinsics-v60-permute.ll2018-03-12 10:01 5.5K 
[ ]swp-phi-chains.ll2018-03-12 11:11 5.6K 
[ ]bank-conflict.mir2018-03-16 16:55 5.7K 
[ ]rdf-filter-defs.ll2018-01-19 12:13 5.8K 
[ ]swp-reuse-phi-6.ll2018-08-02 18:17 5.9K 
[ ]bug19254-ifconv-vec.ll2018-03-12 10:01 6.0K 
[ ]swp-phi.ll2018-03-12 10:01 6.2K 
[ ]wcsrtomb.ll2018-03-12 10:01 6.2K 
[ ]constext-replace.ll2018-03-12 10:01 6.2K 
[ ]addrmode.ll2018-03-12 10:01 6.2K 
[ ]mul64.ll2018-03-12 10:01 6.3K 
[ ]v6vect-no-sideeffects.ll2018-03-12 10:01 6.3K 
[ ]aggr-licm.ll2018-03-12 10:01 6.4K 
[ ]v6vect-dbl.ll2018-03-12 10:01 6.4K 
[ ]reg-scavengebug-2.ll2018-03-12 10:01 6.5K 
[ ]vect-set_cc_v2i32.ll2018-03-12 10:01 6.5K 
[ ]opt-glob-addrs-000.ll2018-03-12 10:01 6.6K 
[ ]opt-addr-mode-subreg-use.ll2018-03-12 10:01 6.6K 
[ ]hexagon-tfr-add.ll2018-03-12 10:01 7.0K 
[ ]rdf-kill-last-op.ll2018-03-12 10:01 7.1K 
[ ]constext-immstore.ll2018-03-12 10:01 7.1K 
[ ]funnel-shift.ll2018-12-20 11:39 7.1K 
[ ]registerscav-missing-spill-slot.ll2018-03-12 10:01 7.1K 
[ ]v6-vecpred-copy.ll2018-03-12 10:01 7.2K 
[ ]swp-reuse-phi-4.ll2018-03-12 10:01 7.4K 
[ ]assert-postinc-ptr-not-value.ll2018-03-12 10:01 7.5K 
[ ]vect-downscale.ll2018-03-26 11:32 7.5K 
[ ]swp-epilog-phi5.ll2018-03-12 10:01 7.6K 
[ ]regscav-wrong-super-sub-regs.ll2018-03-12 10:01 7.7K 
[ ]bug19076.ll2018-03-12 10:01 7.8K 
[ ]opt-glob-addrs-001.ll2018-03-12 10:01 7.8K 
[ ]v6vect-dh1.ll2018-03-12 10:01 7.9K 
[ ]bug14859-iv-cleanup-lpad.ll2018-03-12 10:01 7.9K 
[ ]packetize-impdef.ll2018-03-12 10:01 8.0K 
[ ]misched-top-rptracker-sync.ll2019-01-15 11:18 8.0K 
[ ]P08214.ll2018-03-12 10:01 8.5K 
[ ]jump-prob.ll2018-03-20 15:35 8.6K 
[ ]fltnvjump.ll2018-03-12 10:01 8.6K 
[ ]circ_new.ll2018-03-28 15:38 9.4K 
[ ]v6vect-spill-kill.ll2018-03-12 10:01 9.5K 
[ ]bit-rie.ll2017-10-18 14:07 9.5K 
[ ]swp-conv3x3-nested.ll2018-03-20 15:26 9.6K 
[ ]late_instr.ll2018-03-20 15:35 9.8K 
[ ]vdmpy-halide-test.ll2017-10-18 14:07 10K 
[ ]S3_2op.ll2018-03-19 15:03 10K 
[ ]v6vect-dbl-spill.ll2018-03-12 10:01 10K 
[ ]blockaddr-fpic.ll2018-03-12 10:01 10K 
[ ]hwloop-lt.ll2015-06-17 16:29 10K 
[ ]convert_const_i1_to_i8.ll2018-08-02 18:17 10K 
[ ]SUnit-boundary-prob.ll2018-08-02 18:17 10K 
[ ]v60-vecpred-spill.ll2018-03-12 10:01 11K 
[ ]eliminate-pred-spill.ll2017-10-18 14:07 11K 
[ ]registerscavenger-fail1.ll2018-03-12 10:01 11K 
[ ]hwloop-ne.ll2018-10-19 13:31 11K 
[ ]hwloop-le.ll2018-10-19 13:31 11K 
[ ]regalloc-bad-undef.mir2018-01-31 17:04 11K 
[ ]swp-sigma.ll2018-03-19 15:03 11K 
[ ]frame-offset-overflow.ll2018-03-07 13:53 11K 
[ ]reg-scavengebug-4.ll2018-03-12 10:01 12K 
[ ]verify-sink-code.ll2018-03-12 10:01 12K 
[ ]reg-scavengebug.ll2018-03-12 10:01 12K 
[ ]cext-ice.ll2018-03-12 10:01 12K 
[ ]regscavenger_fail_hwloop.ll2018-03-12 10:01 13K 
[ ]circ_ldd_bug.ll2018-03-06 14:15 13K 
[ ]v60Vasr.ll2017-10-18 14:07 13K 
[ ]expand-vstorerw-undef2.ll2017-10-18 14:07 13K 
[ ]large-number-of-preds.ll2018-03-12 10:01 13K 
[ ]reg-scav-imp-use-dbl-vec.ll2018-03-12 10:01 14K 
[ ]bug14859-split-const-block-addr.ll2018-03-12 10:01 14K 
[ ]intrinsics-v60-vcmp.ll2018-03-12 10:01 14K 
[ ]swp-epilog-phi7.ll2018-03-26 13:53 14K 
[ ]v6-spill1.ll2018-03-12 10:01 14K 
[ ]store-imm-large-stack.ll2017-06-22 10:11 15K 
[ ]lsr-post-inc-cross-use-offsets.ll2018-03-26 13:53 15K 
[ ]reg-scavengebug-5.ll2018-03-12 10:01 15K 
[ ]alu64.ll2017-02-10 10:33 16K 
[ ]vmpa-halide-test.ll2017-10-18 14:07 16K 
[ ]intrinsics-v60-vmpy-acc-128B.ll2018-03-12 10:01 17K 
[ ]intrinsics-v60-vmpy-acc.ll2018-03-12 10:01 18K 
[ ]memops_global.ll2018-03-12 10:01 18K 
[ ]intrinsics-v60-vmpy.ll2018-03-12 10:01 18K 
[ ]swp-loop-carried-crash.ll2018-03-12 10:01 18K 
[ ]opt-glob-addrs-003.ll2018-03-12 10:01 21K 
[ ]intrinsics-v60-misc.ll2018-03-12 10:01 21K 
[ ]regscavengerbug.ll2018-03-12 10:01 21K 
[ ]reg-scavenger-valid-slot.ll2017-10-18 14:07 22K 
[ ]early-if-conversion-bug1.ll2018-01-19 12:13 29K 
[ ]hrc-stack-coloring.ll2018-03-12 10:01 31K 
[ ]intrinsics-v60-alu.ll2018-03-12 10:01 37K 
[ ]concat-vectors-legalize.ll2018-03-12 10:01 43K 
[ ]memops.ll2018-03-06 14:07 45K 
[ ]v60Intrins.ll2018-03-20 15:26 190K